1. Field of the Invention
The invention relates to a method of manufacturing a flash memory cell. More particularly, the present invention relates to a method of manufacturing a flash memory cell capable of preventing an oxidation of a dielectric film between a floating gate and a control gate.
2. Description of the Prior Art
A flash memory cell includes a gate electrode of a stack structure in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are stacked on a given region over a semiconductor substrate, and a junction region on a given region over the semiconductor substrate. A process of manufacturing the flash memory cell will be described below.
The tunnel oxide film and a first polysilicon film are formed on the semiconductor substrate. The first polysilicon film and the tunnel oxide film are then patterned by means of photolithography process and etch process using a given mask. A dielectric film, a second polysilicon film, a tungsten silicide film and a nitride film are formed on the entire structure. The nitride film, the tungsten silicide film, the second polysilicon film and the dielectric film are patterned by means of photolithography process and etch process using a given mask. At this time, the dielectric film has a lower oxide film, a nitride film and an upper oxide film stacked on it. Thereafter, an exposed portion of the first polysilicon film and an exposed portion of the tunnel oxide film are patterned by the self-aligned etch process using the nitride film as an etch mask. Therefore, a gate electrode of a stack structure is formed on the semiconductor substrate. Thereafter, source and drain junction regions are formed in the semiconductor substrate by implanting a low-concentration impurity-ion, forming spacers on sidewalls of the stack gate electrode and implanting a high-concentration impurity-ion.
In the flash memory cell manufactured by the above process, the annealing process is performed to compensate for etch damage caused during the etch process for forming the stack gate and to activate the impurity-ions. When the annealing process is performed, however, the lower and the upper oxide films of the dielectric film are oxidized, thus causing a smiling phenomenon by which the thickness of the dielectric film is increased. As the thickness of the dielectric film is increased, the capacitance is degraded when a gate bias is applied. Thus, there is a problem that the gate-coupling ratio becomes small and the erase speed is accordingly lowered to degrade the characteristic of the device.